This invention relates to a chip package device or unit and to a multi-chip module which comprises a plurality of chip package devices on a printed circuit board used as a mother board. The chip package device is, for example, a CSP (chip size or scale package) device.
Various manners are known on mounting an IC chip on a mother board. For example, Japanese Patent Prepublication (A) No. 288,245 of 1990 discloses a method in which the IC chip is mounted primarily in a facedown or flipchip manner directly on the mother board to provide an IC package according to a COB (chip on board) technique. A plurality of lead wires are preliminarily bonded to the IC chip and are "outer-bonded" to respective bonding lands formed on the mother board with the lead wires preferably fixed onto a polyimide film to provide a lead frame. As another example, Japanese Patent Prepublication (A) No 5,649 of 1987 reveals an IC package having a predetermined number of pins including a power supply pin and a grounding pin and furthermore having a greater number of internal terminals which are connected to an IC chip and to the pins and includes at least one additional power supply terminal and at least one additional grounding terminal.
In any event, an IC chip has a face surface and comprises a plurality of electrodes on the face surface. These electrodes will herein be called facedown electrodes merely for convenience of the description which follows. The facedown electrodes are alternatively called electrodes for flipchip mounting. For mounting such an IC chip, a printed circuit board comprises a plurality of pads surrounding an area on which the IC chip can be supported. The pads are called the bonding lands heretobefore and will hereafter be called board pads. According to the above-cited Patent Prepublication No. 288,245 of 1990, the IC chip is mounted primarily facedown on the printed circuit board with the facedown electrodes electrically bonded to the board pads, respectively, by a plurality of bonding wires used as the lead wires. In this structure, the IC chip is mounted on the mother board in a facedown manner, which is known as a flipchip bonding (FCB) technique. According to the above-referenced Patent Prepublication No. 5,649 of 1987, the IC chip is faceup mounted, with the facedown electrodes connected to the internal terminals by the bonding wires, on a mother board which has the pins and on which the internal electrodes are used as the board pads. In this latter structure, the IC chip will be said to be mounted on the mother board in a wire bonding or bonded manner or structure.
On mounting the IC chip directly on the mother board, it is preferred that such IC chips are known good dice, as called in the art, on each of which all tests are already carried out. It is, however, impossible to perform all tests on each IC chip. This is because it Is difficult to connect the lead wires to each IC chip for automatic control of the tests. If each chip is tested after mounted on the mother board, characteristics of the IC chip may be subjected to changes. This is because the IC chip is usually sealed in a resin overcoat on the mother board. The resin overcoat inevitably applies stress to the IC chip and a piezoelectric effect on its characteristics. It has consequently been the practice on mounting the IC chips on the mother board to take a certain margin into account in order to achieve a desirable yield.
When IC packages are mounted on the mother board, it is readily possible to test each IC package before mounting on the mother board. The wire bonding structure is therefore preferable insofar as the yield is concerned. It should, however, be noted in the manner described above that a conventional IC package has been one of those used in the facedown and the wire bonding manners. This has restricted a freedom in mounting such an IC package on the mother board.
In the meanwhile, a CSP device is recently developed in which the IC chip is covered with a contact or wired sheet which has an inside surface of a slightly greater area than a chip surface of the IC chip. This recent CSP device enables an electronic device small sized and compactly integrated on the mother board with a high integration density. The recent CSP device is for facedown mounting alone. It is difficult to adopt this CSP device to the wire bonding structure although the wire bonding structure provides merits of a raised reliability of visually confirming connection of the bonding wires to the facedown electrodes.
On the other hand, a CSP device is known as will later be described more in detail. In this CSP device which has an overall size of a known barechip in order to attain the high integration density, the contact sheet comprises the facedown electrodes on its outside or obverse surface in a grid-like configuration of a grid pitch of about 0.5 mm. With a solder ball or bump preliminarily formed on each facedown electrode and with the board pads with creamy solder formed on the mother board in correspondence to the facedown electrodes, the solder balls are brought into contact with the creamy solder of the board pads. An assembly of the mother board and such CSP devices is caused to pass through a heated furnace to make up a multi-chip module.
In general, such a CSP device has a fan-in structure in which the facedown electrodes are formed inside an outline of the device. This restricts the grid pitch and the number of the facedown electrodes.
The CSP device has various tasks which must be solved. One of the tasks is to get rid of a difficulty of applying a predetermined amount of the creamy solder to individual board pads. An unbalanced amount results in deterioration in mechanical attachment and electric connection between each CSP device and the mother board. More particularly, it is usual to mount the CSP device on the mother board together with other electronic components, such as resistors. The creamy solder is applied by screen printing. Under these circumstances, it is next to impossible to apply the creamy solder in an amount desirable for respective electronic components including the CSP devices.
Another of the tasks is to remove a difficulty in coping with a temperature cycle to which the multi-chip module is subjected. In more detail, the CSP device has a thermal expansion coefficient which is far smaller than the printed circuit boards. As a result, a damage takes place in a solder mass composed of each solder ball and the creamy solder when the multi-chip module is taken out of the furnace and also when the multi-chip module is subjected thereafter to a change in ambient temperature.
Still another task arises from the fact that the CSP device is for soldering alone. In other words, it is difficult to resort to the COB technique.